As the size of integrated circuit devices has decreased, interconnection contacts that electrically connect elements of the devices have been scaled down. Thus, contact resistance between the interconnection contacts and a conductive layer thereunder (hereinafter, a lower conductive layer) has increased.
To address the increase in contact resistance, the critical dimension (CD), or minimum size, of the interconnection contacts could be expanded. However, as the devices are scaled down, increasing the size of the interconnection contacts may be difficult. Thus, increasing contact area between the interconnection contact and a lower conductive layer, such as a conductive pad, has been considered.
FIG. 1 is a plan view of conventional contact holes 11 and 13 formed between gate lines, and FIG. 2 is a plan view of conventional contact holes 15 formed between bit lines. Referring to FIGS. 1 and 2, as devices become smaller, the sizes of contacts decrease, and the open margins associated with the contact holes 11, 13, and 15 for contacts, such as buried contacts (BCs) and conductive pads realized by self-aligned contacts (SACs), may be reduced, which may lead to an increase in the resistance between contacts, i.e., SAC pads, in the contact holes 11, 13, and 15 and a substrate, and an increased contact resistance between BCs and the SAC pads.
Contacts in DRAM devices may be particularly of interest due to the use of SAC pads formed between gate lines 20 and the BCs formed between the bit lines. In FIG. 1, first contact holes 11 for the SAC pads are formed to have elliptical shapes to increase the size whereas the overall device is scaled down. Similarly, the second contact holes 13 for the conductive pads that electrically connect bit lines to the substrate have elliptical shapes.
Because devices have been scaled down, changing the shapes of the contact holes 11 and 13 may not increase the margins for “opens” associated with the contact holes 11 and 13 sufficiently. As shown in FIG. 1, for about a 96-nm design rule, the bottom margin of each of the contact holes 11 and 13 may be limited to about 40 nm by a spacing between the gate lines 20. The bottom margin of 40 nm may be less than a set size of 120 nm of each of the first contact holes 11.
Referring to FIG. 2, third contact holes 15 for the BCs that electrically connect bit lines to capacitors also have elliptical shapes to increase their open margins. However, for about 96-nm design rules, a bottom margin 15′ of each of the third contact holes 15 is only 80 nm.
The contact resistances may be increased due to the limited margins of the contact holes 11, 13, and 15 at the bottoms thereof. However, it may be difficult to sufficiently increase the bottom margins by increasing the design rule due to reductions in the design rule.
FIG. 3 is a cross-sectional view of the contact holes 11 formed between the gate lines 20 shown in FIG. 1. According to FIG. 3, the bottom margins may be further reduced by etch remnants and native oxides, which may remain on bottoms of the contact holes 11, 13, and 15 as a result of an etch process.
Referring to FIG. 3, the gate lines 20 are formed on a gate oxide layer 21, which is formed on a substrate 10. Also, a gate capping layer 23 and gate spacers 25 are formed on top surfaces and sidewalls of the gate lines 20, respectively, to facilitate a SAC process and a source/drain forming process. In this structure, each of the contact holes 11 which are formed via an insulating layer 30 between the gate lines 20 has a bottom CD of about 40 nm. Here, remnants may be generated while the contact holes 11 are being formed, and native oxides may be formed due to the exposure of the substrate 10. Thus, the remnant or the native oxides may remain on the substrate 10 as a resistive layer 17.
Although it may be possible to remove the resistive layer 17 by a cleaning process, the cleaning efficiency may be relatively low. Also, since a portion of the surface of the substrate 10 exposed by an etch process may be rough, it may be difficult to completely remove the resistive layer 17. Thus, the resistive layer 17 may cause adverse effects, such as reduction of the bottom CDs. As a result, the resistive layer 17 may increase contact resistance.